1. Field of the Invention
The invention relates to a digitally controlled oscillator (DCO) and, in particular, to a method of frequency search for the DCO.
2. Description of the Related Art
With advances in deep-submicron technology, demand for high-performance and short time-to-market integrated circuits has dramatically grown. Scalable microprocessor and graphic-processor systems can be cost-effectively ported to advanced technologies to increase clocking rate, lower power dissipation, and reduce design turn-around time. Synchronization among IC modules has become critical. Thus, considerable effort has been focused on high-performance digital interface circuits to communicate with these digital systems. A digital PLL can migrate over different processes. Moreover, with benefits from scaling CMOS technologies, the digital PLL has a lower supply voltage and potential for improved power management.
FIG. 1 is a block diagram of a conventional digital PLL 100 comprising a time to digital converter (TDC) 110, a low pass filter (LF) 120, a digitally controlled oscillator (DCO) 130, and a divider 140. The time to digital converter (TDC) 110 receives a reference clock signal and converts the same to a digital signal. The low pass filter (LF) 120 receives the digital signal and generates a control code. The digitally controlled oscillator (DCO) 130 receives the control code to control an output frequency of an output signal. The output signal of the DCO 130 is received by the divider 140 and then fed back to the TDC 110.
FIG. 2A is a diagram of period (inverse of frequency) versus an output code of the low pass filter in a conventional digital PLL with a DCO. FIG. 2B is a diagram of period (inverse of frequency) versus a control code for the DCO in a conventional digital PLL with a DCO with non-overlapped sub-bands. However, for such digital PLLs, each output code of the low pass filter in FIG. 2A corresponds to a control code for the DCO in FIG. 2B. Referring to FIG. 2B, the digital PLL with the DCO with non-overlapped sub-bands suffers large frequency jump or frequency dead zones on boundaries of sub-bands.
FIG. 3A is a diagram of period (inverse of frequency) versus an output code of the low pass filter in a conventional digital PLL. FIG. 3B is a diagram of period (inverse of frequency) versus a control code for the DCO in a conventional digital PLL with a DCO with overlapped sub-bands. However, for such digital PLLs, each output code of the low pass filter in FIG. 3A corresponds to a control code for the DCO in FIG. 3B. Referring to FIG. 3B, the digital PLL with the DCO with overlapped sub-bands still suffers frequency dead zones on boundaries of sub-bands and is thus unable to accomplish frequency lock.